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Last update: 21 september 2020 | SRPMs: 17690 | Visits: 19263237
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Group :: Engineering
RPM: verilator

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Current version: 3.924-alt1.2
Build date: 18 april 2020, 14:31 ( 22.3 weeks ago )
Size: 1017.60 Kb

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License: LGPLv3 or Perl Artistic 2.0
Summary: A fast and free Verilog HDL simulator

Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and
Synthesis assertions into C++ or SystemC code. It is designed for large projects
where fast simulation performance is of primary concern, and is especially well
suited to generate executable models of CPUs for embedded software design teams.

Current maintainer: Michael Shigorin

List of contributors

List of rpms provided by this srpm:

  • verilator
  • verilator-debuginfo
  • verilator-doc
    design & coding: Vladimir Lettiev aka crux © 2004-2005, Andrew Avramenko aka liks © 2007-2008
    current maintainer: Michael Shigorin