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RPM: iverilog
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Current version: 12.0-alt1
Build date: 10 january 2023, 16:14 ( 66.5 weeks ago )
Size: 1942.54 Kb
Home page: http://iverilog.icarus.com
License: GPLv2
Summary: Verilog simulation and synthesis tool
Description:
List of contributors List of rpms provided by this srpm:
ACL:
Build date: 10 january 2023, 16:14 ( 66.5 weeks ago )
Size: 1942.54 Kb
Home page: http://iverilog.icarus.com
License: GPLv2
Summary: Verilog simulation and synthesis tool
Description:
Icarus Verilog is a Verilog simulation and synthesis tool. It operates
as a compiler, compiling source code written in Verilog (IEEE-1364)
into some target format. For batch simulation, the compiler can generate
an intermediate form called vvp assembly. This intermediate form is
executed by the ``vvp'' command. For synthesis, the compiler generates
netlists in the desired format. It supports the 1995, 2001 and 2005
versions of the standard, portions of SystemVerilog, and some extensions.
Current maintainer: Egor Ignatov as a compiler, compiling source code written in Verilog (IEEE-1364)
into some target format. For batch simulation, the compiler can generate
an intermediate form called vvp assembly. This intermediate form is
executed by the ``vvp'' command. For synthesis, the compiler generates
netlists in the desired format. It supports the 1995, 2001 and 2005
versions of the standard, portions of SystemVerilog, and some extensions.
List of contributors List of rpms provided by this srpm:
- iverilog
- iverilog-debuginfo