Sisyphus repository
Last update: 7 may 2021 | SRPMs: 17693 | Visits: 20887276
en ru br
ALT Linux repos

Group :: Engineering
RPM: verilator

 Main   Changelog   Spec   Patches   Sources   Download   Gear   Bugs and FR  Repocop 

Current version: 4.200-alt1
Build date: 20 april 2021, 14:32 ( 2.5 weeks ago )
Size: 1519.29 Kb

Home page:

License: LGPLv3 or Perl Artistic 2.0
Summary: A fast and free Verilog HDL simulator

Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and
Synthesis assertions into C++ or SystemC code. It is designed for large projects
where fast simulation performance is of primary concern, and is especially well
suited to generate executable models of CPUs for embedded software design teams.

Current maintainer: Egor Ignatov

List of contributors

List of rpms provided by this srpm:

  • verilator
  • verilator-debuginfo
  • verilator-doc
    design & coding: Vladimir Lettiev aka crux © 2004-2005, Andrew Avramenko aka liks © 2007-2008
    current maintainer: Michael Shigorin