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S:3.924-alt1

Group :: Engineering
RPM: verilator

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Current version: 3.924-alt1
Build date: 22 june 2018, 02:15 ( 51.4 weeks ago )
Size: 1016.68 Kb

Home page:   https://www.veripool.org/wiki/verilator

License: LGPLv3 or Perl Artistic 2.0
Summary: A fast and free Verilog HDL simulator
Description:

Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and
Synthesis assertions into C++ or SystemC code. It is designed for large projects
where fast simulation performance is of primary concern, and is especially well
suited to generate executable models of CPUs for embedded software design teams.

Current maintainer: Elvira Khabirova

List of contributors

List of rpms provided by this srpm:

  • verilator
  • verilator-debuginfo
  • verilator-doc
ACL:
     
    design & coding: Vladimir Lettiev aka crux © 2004-2005, Andrew Avramenko aka liks © 2007-2008
    current maintainer: Michael Shigorin